1. Field of the Invention
This invention relates to a row decoder for a semiconductor memory device.
2. Description of the Prior Art
FIG. 1 illustrates a row decoder used in a semiconductor memory device. The row decoder of FIG. 1 includes a predecoder 1 comprising CMOS (Complementary Metal-Oxide Semiconductor) type NAND circuits 4, and a main decoder 2 comprising CMOS type NOR circuits 5. The output of each of the NAND circuit 4 is connected to a plurality of the NOR circuits 5. The outputs of the NOR circuits 5 are connected to a memory cell array 3 through word lines (W.L.) 6. The outputs of NOR circuits 5 connected to the two NAND circuits 4 shown in FIG. 1 are respectively referenced by a to h. As shown in FIG. 2, each of the NAND circuits 4 has P-channel transistors 21, 22, 23, . . . connected in parallel, and N-channel transistors 31, 32, 33, . . . connected in series. From the standpoints of a balance of the rising and falling rates of the output and also of a margin for noise, the (channel width)/(channel length) ratio (hereinafter abbreviated as W/L ratio) of the N-channel transistors 31, 32, 33, . . . is greater than the W/L ratio of the P-channel transistors 21, 22, 23, . . . From similar standpoints, in each of the NOR circuits 5 which, as shown in FIG. 3, has P-channel transistors 41, 42, 43, . . . connected in series and N-channel transistors 51, 52, 53, . . . in parallel, the W/L ratio of the P-channel transistors 41, 42, 43, . . . is greater than the W/L ratio of the N-channel transistors 51, 52, 53, . . .
As mentioned above, in the NAND circuit 4 shown in FIG. 2, the W/L ratio of the N-channel transistors 31, 32, 33, . . . is greater than the W/L ratio of the P-channel transistors 21, 22, 23, . . . When, for example, an input signal 11 is LOW and other input signals 12, 13, . . . are HIGH and the state of the input signal 11 transfers from LOW to HIGH, therefore, the turn-on of the N-channel transistor 31 to which the input signal 11 is applied is faster than the turn-off of the P-channel transistor 21 to which the same input signal 11 is applied. Consequently, the transition from HIGH to LOW of an output signal A of the NAND circuit 4 is faster than that in the case where the W/L ratio of the N-channel transistors 31, 32, 33, . . . is not greater than the W/L ratio of the P-channel transistors 21, 22, 23, . . . By contrast, in the NOR circuit 5 shown in FIG. 3, the W/L ratio of the P-channel transistors 41, 42, 43, . . . is greater than the W/L ratio of the N-channel transistors 51, 52, 53, . . . When, for example, an input signal 101 is HIGH and other input signals 102, 103, . . . are LOW and the state of the input signal 101 transfers from HIGH to LOW, therefore, the transition from LOW to HIGH of an output signal B of the NOR circuit 5 is faster than that in the case where the W/L ratio of the P-channel transistors 41, 42, 43, . . . is not greater than the W/L ratio of the N-channel transistors 51, 52, 53, . . . When the NAND circuit 4 and NOR circuit 5 operate in succession so as to perform the function of a row decoder, therefore, the transition from LOW to HIGH of the output signal B is relatively fast.
On the other hand, when all of the input signals 11, 12, 13, . . . to the NAND circuit 4 are HIGH and the state of one of the input signals transfers from HIGH to LOW, the transition from LOW to HIGH of the output signal A from the NAND circuit 4 is relatively slow. When all of the input signals 101, 102, 103, . . . applied to the NOR circuit 5 are LOW and the state of one of the input signals transfers from LOW to HIGH, the transition from HIGH to LOW of the output signal B from the NOR circuit 5 is relatively slow. When the NAND circuit 4 and NOR circuit 5 operate in succession so as to perform the function of a row decoder, therefore, the transition from HIGH to LOW of the output signal B is relatively slow.
As seen from the above description, in a prior art row decoder, the transition from LOW to HIGH of the output signal is fast (e.g., the output a), while the transition of the output signal from HIGH to LOW is slow (e.g., the output e). As shown in FIG. 5, therefore, a prior art row decoder involves a problem in that the overlap T.sub.1 of the transient periods of different output signals is comparatively long, which may lead to the trouble of the double selection of memory cells, resulting in that the storage contents are thus possibly destroyed.